Is NVIDIA Doubling Down On RISC-V?

For years NVIDIA has built its reputation on specialized graphic processing cards (GPU). The US chip giant now appears to be exploring the terrain beyond GPU architecture, raising the stakes on other dedicated electronic circuits. Synced recently observed a series of job postings seeking experts in RISC-V and posted on LinkedIn, WeChat and other platforms. The offers are from NVIDIA.

RISC-V (“reduced instruction set computer – five”) is a freely available open-source microprocessor instruction set architecture (ISA) that has always been of academic interest. In recent years the emerging hardware architecture has also been garnering widespread industry attention, with NVIDIA as one of the stakeholders.

Six RISC-V positions have been advertised by NVIDIA, based in Shanghai and pertaining to architecture, design, and verification:

• Senior CPU Architecture Engineer (RISC-V / Security);
• Senior Video Codec Architecture Engineer;
• Senior Video Codec IC Design Engineer;
• Senior CPU Design Engineer (RISC-V / Security);
• Senior IC Verification Engineer (Image Processing ISP)
• Senior IC Verification Engineer (Video Codec).

It’s noteworthy that the job posting for Senior CPU Architecture Engineer stipulates “Applicants should have in-depth understanding of the application scenarios of different subsystems in NVIDIA GPUs and define the architecture for NVIDIA RISC-V processor.” According to another LinkedIn job posting, RISC-V processors will be embedded into NVIDIA GPU and Tegra SoC.

NVIDIA is also seeking Senior CPU Design Engineer candidates who can “participate in the design and implementation of NVIDIA’s next-generation RISC-V CPU for security.”

The budding interest in RISC-V can be attributed to the slowing growth of general-purpose compute performance, according to James Prior, global head of communications at SiFive, a leading provider of commercial RISC-V processor IP and silicon solutions.

“The rapid evolution of compute workloads requires domain specific architectures to ensure continued performance scaling over time. The solution to this problem is an open-source, extensible standard that permits the development of domain specific application processors,” Prior told Synced.

Due its light weight and extensibility, RISC-V is gaining mainstream adoption across many new sectors, including datacenter accelerators, mobile & wireless, automotive, and IoT, Prior added.

Along with other major industry players Google, Samsung, IBM, and Qualcomm, NVIDIA is a member of the RISC-V Foundation, and has long supported RISC-V development. In 2016 the company unveiled plans to replace the internal micro-controllers of their graphic cards with next-gen RISC-V-based controllers built for upcoming NVIDIA GPUs.

Introduced in 2005, Falcon (FAst Logic CONtroller) is a class of general-purpose embedded micro-controllers for NVIDIA GPUs. While not as important as the GPU cores, Falcon units take on a variety of roles ranging from video decoding to memory copying to security.

In a 2017 RISC-V workshop in Shanghai, NVIDIA explained that shortcomings such as low performance and lack of caches and thread protection meant Falcon’s architecture could not meet growing complexity demands.

NVIDIA listed the technical criteria for its next-gen architecture: more than twice the performance of Falcon, less than twice the area cost of Falcon, support for caches, tightly coupled memories, 64-bit addresses, and suitability for modern operating systems. They concluded only RISC-V meets all criteria. The new RISC-V micro-controllers will outperform Falcon micro-controllers by three times, Tom’s Hardware has reported.

Another advantage of RISC-V is that its ISA is open-sourced, so anyone is free to develop proprietary or open source implementations for commercial or other exploitations on top of it, says Microsoft Senior Electrical Engineer Chulian Zhang. “Free use is a big consideration for implementing RISC-V, and today there are many who support, participate in and use RISC-V.”

NVIDIA is also using RISC-V processors in many of its products beyond GPUs. Earlier this year, PCGames reported that NVIDIA is developing aprototype multi-die AI accelerator chip, RC 18. The 16-nm chip comprises 16 PEs (Processing Elements), a basic RISC-V Rocket CPU core, buffer memory, and eight GRS (Ground-Referenced Signaling) links.

While preparing this story Synced asked NVIDIA if it had any updates related to potential RISC-V deployment, but the company declined to comment.

An increasing number of major industry players are doubling down on RISC-V. For example, US data storage giant Western Digital this year announced a new open source RISC-V CPU core along with two additional RISC-V innovations. Chinese tech behemoth Alibaba has introduced an RISC-V processor as a core IP to produce high-end edge-based micro-controllers (MCUs), CPUs, and SoC. And this June, Qualcomm joined a US$65.4 million investment in SiFive.

“RISC-V is the Linux of processors,” says Thomas J Riordan, outside director at Mellanox Technologies. Riordan believes building a complete software system will be the biggest challenge before RISC-V implementation becomes viable across the chip design industry.

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Journalist: Tony Peng | Editor: Michael Sarazen